In recent years, many innovative technologies and new cell structures for high concentration flash memories have been published for instance contactless cell array with F-N tunneling erase/write operation.
FIG. 5 illustrates a cross-sectional view of a conventional involatile semiconductor memory device. Incidentally, this is described in a literature named "An Asymmetrical Offset Source/Drain Structure for Virtual Ground Array Memory with DINOR Operation" by "Symposium on VLSI Technology", pp 57-58, 1993. As shown FIG. 5, in this conventional involatile semiconductor memory device, a composite gate is provided on the surface of a p-type semiconductor substrate 1, on which a first gate insulating film 2, a floating gate 3, a second gate insulating film 4 and a control gate 5 are each sequentially layered.
Further, in the conventional involatile semiconductor memory device, an n.sup.+ -type diffusion layer 8 is provided on the surface of the p-type semiconductor substrate 1, the n.sup.+ -type diffusion layer 8 overlapping with the end of one adjacent floating gate 3 and being spaced apart from the other end of the floating gate 3 by a non-doped offset area 6. The control gates 5 are interconnected to form a word line, and the n.sup.+ -type diffusion layer 8 is formed as a bit line/source line, to form a memory cell array.
As described above, in the memory cell array, the diffusion layer of the source or drain of the adjacent memory cells are integrally formed with the diffusion layer extending perpendicular to the direction in which the channel of the memory cell extends taken as the bit line/source line and with the control gate interconnected in the direction in which the channel of the adjacent memory cell extends to form the word line, and it is called a "virtual ground memory cell array". The advantage of this virtual ground memory cell array is that the bit line is arranged with the diffusion layer and that no contact is necessary to connect the drain and the bit line to each memory cell unlike the case in which the bit line is arranged with the metallic line, which allows the area of the memory cell to be made small.
Referring now to an equivalent circuit of the virtual ground memory array of FIG. 6, erasure, writing and reading operations of the virtual ground memory cell array are described.
A erasure operation of the memory cell is conducted for each word line and is operated by the next described sequence. (1) A positive high voltage is applied to a selected word line, for example, W.sub.1. (2) Electron is injected from the p-type semiconductor substrate 1 to the floating gate 3 through the first gate insulating film 2 in the form of a Fowler Nordheim tunnel (hereinafter referred to as "F-N tunnel") to set the threshold voltage of the memory cells M.sub.i, k-1, M.sub.i, k, M.sub.i, k+l on the selected word line W.sub.i to, for example, about 5 V.
A writing operation into the memory cell M.sub.i, k is conducted in the following sequence. (1) A negative voltage of, for example, -9 V is applied to the word line W.sub.i. (2) Other word lines W.sub.i-1, W.sub.i+1 are set to the ground potential. (3) A positive voltage of, for example, 5 V as a writing data of the memory cell M.sub.i, k is applied to the bit line b.sub.k. (4) Other bit lines b.sub.k-1 , b.sub.k+1, b.sub.k+2 are set to the floating potential. (5) The electron accumulated to the floating gate of the memory cell M.sub.i, k are discharged the way of the F-N tunnel to the bit line b.sub.k through the F-N tunnel, and the threshold voltage of the memory cell M.sub.i, k is set to, for example, about 1 V.
Incidentally, during this writing, since there is an offset between the floating gate and the bit line b.sub.k of the adjacent memory cells M.sub.i, k-1, neither the electrons of the floating gate of the memory cell M.sub.i, k-1 discharged to the bit line b.sub.k through the FN tunnel, nor is written to the memory cell M.sub.i, k-1.
A reading operation of the memory cell M.sub.i, k is conducted in the following sequence. (1) A power source voltage Vcc of, for example, 3 V is a applied to the word line W.sub.i. (2) Other word lines W.sub.i-1, , W.sub.i+ 1 are set to the ground potential. (3) The bit line b.sub.k is set to the ground potential. (4) The reading voltage of, for example, 1 V is applied to the bit line b.sub.k+1. (5) Other bit lines b.sub.k-1, b.sub.k+2 are set to the floating potential. (6) The data of the memory cell M.sub.i, k is read from the bit line b.sub.k+1.
Incidentally, in a conventional involatile semiconductor memory device having the virtual ground memory cell array, during the reading operation, a resistance element made of an impurity which lies at the side of the drain of the drain cell is added to the non-doped offset area 6, and the reading current becomes small. Therefore the reading current becomes small, then it becomes impossible to read data at a fast speed.